Programmable logic devices (“PLDs”) are a well-known type of integrated circuit that can be programmed to perform specified logic functions. One type of PLD, the field programmable gate array (“FPGA”), typically includes an array of programmable tiles. These programmable tiles can include, for example, input/output blocks (“IOBs”), configurable logic blocks (“CLBs”), dedicated random access memory blocks (“BRAMs”), multipliers, digital signal processing blocks (“DSPs”), processors, clock managers, delay lock loops (“DLLs”), and so forth. Notably, as used herein, “include” and “including” mean including without limitation. One such FPGA, the Xilinx Virtex® FPGA, is available from Xilinx, Inc., 2100 Logic Drive, San Jose, Calif. 95124.
Another type of PLD is the Complex Programmable Logic Device (“CPLD”). A CPLD includes two or more “function blocks” connected together and to input/output (“I/O”) resources by an interconnect switch matrix. Each function block of the CPLD includes a two-level AND/OR structure similar to those used in Programmable Logic Arrays (“PLAs”) and Programmable Array Logic (“PAL”) devices. Other PLDs are programmed by applying a processing layer, such as a metal layer, that programmably interconnects the various elements on the device. These PLDs are known as mask programmable devices. PLDs can also be implemented in other ways, for example, using fuse or antifuse technology. The terms “PLD” and “programmable logic device” include but are not limited to these exemplary devices, as well as encompassing devices that are only partially programmable.
For purposes of clarity, FPGAs are described below though other types of PLDs may be used. FPGAs may include one or more embedded microprocessors. For example, an embedded microprocessor may be located in an area reserved for it, generally referred to as a “processor block.”
Heretofore, a software tool used to instantiate a processor-based design in a PLD, such as an FPGA, assigned address ranges for coupling circuit blocks (“peripherals”) to a processor, such as with an embedded or instantiated processor, on a random basis subject to availability. Accordingly, if a design was changed, then on a subsequent instantiation of the design in a PLD, the address ranges would be reassigned by such software tool. Conventionally, this meant that one or more of the address ranges would change from an initial instantiation of a design to an instantiation of a revision of the design. This variability is a consequence of the flexibility of the PLD platform. However, such variability, especially when not used by a user, makes the task of managing designs more complex and error prone as each instantiation could have different addressing of peripherals. It should be understood that heretofore two identical systems which would be independently designed may yield different address maps for coupling to a bus or buses. Such variability was dependent on the particular PLD platform, the Embedded Developer Kit (“EDK”) software tool or tools, or the printed circuit board (“PCB”). As is well-known, a microprocessor accesses memory and I/O via addresses. For a microprocessor to access memory or an I/O device, conventionally such microprocessor places an address for the device on an address bus coupled to the device, along with a read or write instruction on a control bus for the device
In contrast to a system-on-chip implementation in a PLD, an Application Specific Integrated Circuit (“ASIC”) or Application Specific Standard Product (“ASSP”) dedicated system-on-chip integrated circuits with built in peripherals, such as a PowerPC 405GP from International Business Machines (“IBM)” of New York for example, have addresses that are fixedly assigned by the manufacturer.
Accordingly, it would be desirable and useful to provide means that facilitate yielding a same address map for similarly situated peripherals of same or different systems regardless of the EDK software version used, PLD used, or PCB used, or any combination thereof, for instantiation of a system design on a PLD.